The present invention relates to a process for preparation of a SONOS flash memory device including an ONO structure in which the bottom oxide layer exhibits reduced charge leakage. The bottom oxide layer is provided with increased oxygen content and/or reduced oxygen vacancy content.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. One EEPROM device that utilizes the ONO structure is a silicon-oxide-nitride-oxide-silicon (SONOS) type cell. A second EEPROM device that utilizes the ONO structure is a floating gate FLASH memory device, in which the ONO structure is formed over the floating gate, typically a polysilicon floating gate.
In SONOS devices, during programming, electrical charge is transferred from the substrate to the silicon nitride charge storage layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom oxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride charge storage layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer, in addition to storing charge in a single region of the charge storage layer. This type of non-volatile memory device is known as a dual-bit EEPROM, which is available under the trademark MIRRORBIT(trademark) from Advanced Micro Devices, Inc., Sunnyvale, Calif. The MIRRORBIT(trademark) dual-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left bit and a right bit are stored in physically different areas of the silicon nitride layer, in left and right regions of each memory cell, respectively. Programming methods are then used that enable the two bits to be programmed and read simultaneously. Each of the two bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions. In recent developments, multi-bit memory cells have been developed, in which more than two bits can be stored in separate regions of a single memory cell.
The control gate electrode is separated from the charge storage layer by a top dielectric layer, and the charge storage layer is separated from the semiconductor substrate (channel region) by the bottom dielectric layer, forming the oxide-nitride-oxide stack, i.e., the ONO structure or layer. As device dimensions continue to be reduced, the electrical thickness of the top and bottom dielectric layers must be reduced accordingly. Previously, this has been accomplished by scaling down the thickness of the ONO layer. However, as the ONO layer is made physically thinner, leakage currents through the ONO layer may increase, which limits the scaling down of the total physical thickness of the ONO layer. Thus, it becomes more and more important to provide high quality oxide layers, and particularly a high quality bottom oxide layer, free of defects such as oxygen vacancies, Exe2x80x2 centers and dangling bonds.
Some of the improvements in devices can be addressed through development of materials and processes for fabricating the ONO layer. Recently, development efforts have focused on novel processes for fabrication of the ONO layer. While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using dual-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, the bottom oxide layer of the ONO structure must be carefully fabricated to avoid the creation of interface states that could provide charge leakage paths from the charge storage layer into the substrate. Accordingly, advances in ONO fabrication technology are needed to insure proper charge isolation in ONO structures used, for example, in MIRRORBIT(trademark) dual-bit EEPROM devices.
The present invention, in one embodiment, relates to a process for fabricating a SONOS flash memory device having reduced charge leakage, including: providing a semiconductor substrate; forming a bottom oxide layer of an ONO structure on the semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer.
In another embodiment, the present invention relates to a process for fabricating a SONOS flash memory device having reduced charge leakage, including: providing a semiconductor substrate; forming a bottom oxide layer of an ONO structure on the semiconductor substrate by a highly oxidizing process, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.
In another embodiment, the present invention relates to a SONOS flash memory device, including: a semiconductor substrate; an ONO structure on the semiconductor substrate, the ONO structure including a bottom oxide layer, a dielectric charge storage layer and a top oxide layer, the bottom oxide layer having a super-stoichiometric oxygen content and an oxygen vacancy content of substantially zero, wherein the bottom oxide layer exhibits a reduced charge leakage relative to a bottom oxide layer having a stoichiometric or sub-stoichiometric oxygen content and a substantial number of oxygen vacancies.
Thus, according to the present invention, by providing an increased oxygen content in the bottom oxide layer of the ONO structure in a flash memory device, a bottom oxide layer may be fabricated without creation of interface states resulting from oxygen vacancies, Exe2x80x2 centers and dangling bonds, which could provide charge leakage paths from the charge-storage layer. The present invention can be carried out in a cluster tool. The present invention provides advantages such as (1) formation of a bottom oxide layer with a higher oxygen content and a reduced oxygen vacancy content, reduced numbers of Exe2x80x2 centers and dangling bonds; (2) allowing selection of any of a number of different methods for obtaining advantage (1); (3) a lower thermal budget; (4) formation of a bottom oxide layer having fewer interface states that could provide charge leakage paths; and (5) formation of an ONO structure with improved charge storage capability. Thus, the present invention provides an advance in ONO fabrication technology, and insures proper charge isolation in ONO structures used in MIRRORBIT(trademark) dual-bit EEPROM devices, while at the same time providing distinct process and economic advantages. Although described in terms of, and particularly applicable to, MIRRORBIT(trademark) dual-bit EEPROM devices, the present invention is broadly applicable to fabrication of any semiconductor device that includes an ONO structure.